The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include sequential deposition of conductive and insulative layers on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove material from one or more conducting layers from the areas not covered by the mask, thereby etching the conducting layer or layers in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. Additional techniques, such as dual damascene processes, are used to form conductive vias which establish electrical contact between vertically-spaced conductive lines or layers in the circuits. The finished semiconductor product includes microelectronic devices including transistors, capacitors and resistors that form the integrated circuits on each of multiple die on a single wafer.
In the semiconductor industry, CMOS (complementary metal-oxide semiconductor) technology is extensively used in the fabrication of IC devices. CMOS technology typically involves the use of overlying layers of semiconductor material with the bottom layer being a dielectric layer and the top layer being a layer of doped silicon material that serves as a low-resistivity electrical contact gate electrode. The gate electrode, also referred to as a gate stack, typically overlies the dielectric layer.
In the semiconductor fabrication industry, silicon oxide (SiO2) is frequently used for its insulating properties as a gate oxide or dielectric. As the dimensions of device circuits on substrates become increasingly smaller, the gate dielectric thickness must decrease proportionately in field effect transistors (FETs) to approximately 3 to 3.5 nonometers. Accordingly, device performance and reliability can be adversely affected by such factors as interfacial defects, defect precursors and diffusion of dopants through gate dielectrics, as well as unintended variations in thickness in the gate oxide layer among central and peripheral regions of the layer.
Two types of CMOS device structures which are commonly fabricated in semiconductor technology include the MOSCAP (metal oxide semiconductor capacitor) structure and the MOSFET (metal oxide semiconductor field effect transistor) structure. Both of these structures include a substrate on which is deposited a dielectric layer having a high dielectric constant (k), such as a pad oxide layer. A silicon-containing gate, or gate stack, is deposited on the dielectric layer and connects a pair of trench oxide layers (in the case of a MOSCAP structure) or source and drain regions (in the case of a MOSFET structure).
FIG. 1 is a cross-section of an example of a polysilicon gate 20 formed between a source 16 and a drain 18 of a device 30 on a semiconductor wafer substrate 10. An STI (shallow trench isolation) structure 32 includes a shallow trench 12 filled with oxide 14 and separates devices from each other on the wafer substrate 10. A polysilicon silicide, or polycide 22, typically composed of nickel or cobalt, is deposited on the polysilicon gate 20, and an insulating layer 28 is deposited on the polycide 22. A source silicide 24 is deposited on the source 16, and a drain silicide 26 is deposited on the drain 18.
As shown in FIG. 2, an STI structure 36 is fabricated by initially depositing a pad oxide layer 42 on a silicon substrate 40 and a silicon nitride layer 44 on the pad oxide layer 42. One or more trenches 38 is etched through the silicon nitride layer 44 and the pad oxide layer 42, into the substrate 40. A liner oxide layer 46 is then deposited on the sidewalls and bottom of the trench or trenches 38. After a liner densification step, each trench 38 is filled with a trench oxide 48, followed by chemical mechanical planarization of the oxide layer 50 above the trench oxides 48.
The profile of the STI trench 38 is critical for proper CMOS transistor operation. The shape of the top corners 52 of the trench 38 impacts the inverse narrow width effect (INWE), as well as the gate oxide integrity (GOI). The shape of the bottom corners 54 is closely related to junction leakage. Additionally, dopant segregation and STI stress control are important for optimum device performance and reliability.
Conventional methods of suppressing the INWE have included tilted sidewall implantation and edge implantation. Furthermore, shallow trench isolation using nitric oxide-annealed liner oxide layer has been shown to prevent out-diffusion of boron through the liner oxide layer. For stress control of STI processing, oxide-nitride layers or a triple layer of oxide-nitride-oxide have been used to relieve STI stress.
From a production point of view, tilted sidewall implantation and edge implantation suffer from the disadvantage of requiring additional photolithographic work to protect the pmos region. Furthermore, while it is a relatively simple method, shallow trench isolation using nitric oxide-annealed liner oxide layer results in a liner oxide layer in which the nitrogen concentration is very low (<2%). Thus, the improvement in restriction of boron out-diffusion is low. Finally, the use of oxide-nitride layers or a triple layer of oxide-nitride-oxide as the liner oxide layer results in a liner oxide layer which is rather thick (in the range of 200˜600 angstroms). This thickness is excessive for sub-micron technology. Additionally, the pad removal step causes phosphoric acid to recess the nitride layer, forming a gap which leads to an unacceptably large void in the layer. Accordingly, a new and improved STI liner modification method is needed which optimizes STI trench corner rounding, retards dopant segregation into a liner oxide layer and reduces the STI stress affect during STI fabrication.
An object of the present invention is to provide a new and improved STI liner modification method for a liner oxide layer in an STI trench.
Another object of the present invention is to provide a new and improved liner modification method which optimizes corner faceting of an STI trench.
Still another object of the present invention is to provide a new and improved liner modification method which optimizes the inverse narrow width effect (INWE) and gate oxide integrity (GOI) of a semiconductor device, enhancing device performance.
Yet another object of the present invention is to provide a new and improved liner modification method which is effective in controlling the nitrogen profile and concentration in a liner oxide layer of an STI structure in order to prevent diffusion of dopant into the liner oxide layer, thus controlling the INWE.
A still further object of the present invention is to provide a new and improved liner modification method by which a high concentration of nitrogen can be introduced into a liner oxide layer in an STI trench for enhanced STI stress management, facilitating enhanced device performance.
Another object of the present invention is to provide a new and improved liner modification method which typically does not require additional lithography steps beyond the usual lithography steps required to fabricate a shallow trench isolation structure.
Another object of the present invention is to provide a new and improved liner modification method which includes etching of an STI trench in a substrate and formation of a liner oxide layer on the trench surfaces by an oxidation process, and which method further includes pre-treatment of the trench surfaces with nitrogen prior to formation of the layer, post-formation nitridation of the layer, or both.